The increasing demand of such reduced size large capacity computer with a high operating speed necessitates use of a semiconductor chip with a high integration density, such as a semiconductor chip of 10 mm square having more than 500 contacts, terminals or pins on its entire front face and more than 10W/chip heat radiation during operation and use of a multi-layered organic circuit board having a small or low dielectric constant for mounting such semiconductor chips with a high density.
The conventional semiconductor chip package having a good thermal conductivity such as a flat package and a pin grid array package are limited of their terminal number below 500, because they are taken out from the four sides of the semiconductor chip and further the substrate supporting the terminals becomes necessarily larger than the semiconductor chip, a high density mounting of such semiconductor chip packages on a multi-layered circuit board is rendered impossible.
The dielectric constant of a multi-layered organic circuit board is small in comparison with that of a ceramic insulating material. Even silica (SiO.sub.2), which has a comparatively small dielectric constant among ceramic insulating material, has a dielectric constant of about 4. In contrast, the dielectric constant of a fluorine resin can be as small as 2.5. The dielectric constant of multi-layered organic circuit board which is mass produced at present is as small as 4.5. It is therefore possible to reduce the delay in signal propagation by using such multi-layered organic circuit board. Moreover it is possible to produce a large-sized multi-layered circuit board with a high precision by an organic material. It is therefore possible to mount a large number of semiconductor chips on such multi-layered organic circuit board.
However, the thermal expansion coefficient of such multi-layered organic circuit board is as large as 150 to 250.times.10.sup.-7 /.degree.C. On the other hand, those of silicon semiconductor chip and of gallium arsenide semiconductor chip are respectively 35.times.10.sup.-7 /.degree.C. and 60.times.10.sup.-7 /.degree.C. Moreover the increase of the contact number more than 500 on the front face of the semiconductor chip makes the spacing between the adjacent contacts small such that the soldering area on the respective contacts for electrical connection is also rendered small. It is therefore impracticable to mount the semiconductor chips directly on the multi-layered organic circuit board by soldering, because the solder joints connecting the corresponding contacts breaks due to the large thermal expansion coefficient difference and the small soldering area.
A multi-layered circuit board and a ceramic substrate carrying semiconductor chips thereon and having a different thermal expansion coefficient from that of the circuit board were conventionally bonded by a so-called connector comprising a pair of engage-and disengageable contacts. However, in the case of using the connector, the spacing or pitch between adjacent contacts or terminals is limited to 1 mm, and the connection at a pitch of 0.5 mm or below was impossible.
Japanese Patent Application Laid-Open No. 60-257156 discloses a semiconductor chip module including a plurality of semiconductor chips, each having contacts on its entire front face, a first ceramic circuit board mounting the semiconductor chips thereon though a connecting solder and a second circuit board carrying an auxiliary circuit and connected with the first ceramic circuit board through the so-called engage-and disengageable connectors. Since the disclosed semiconductor chip module uses the ceramic circuit board, which has a comparatively high dielectric constant, the delay in signal propagation in the semiconductor chip mounting member of the semiconductor chip module is considered substantial.